MBIST, ATPG, Dft, Scan Insertion, Siemens Tessent, DFT Simulation

bist , boundary scan , Jtag, test compression, ATPG, EDA Tools, Scan Insertion, DFT methodologies, Logic Memory, Synopsys TestMAX, Mentor Tessent

Jtag, Perl, Python, NVIDIA custom tools, Memory BIST, SV, ATPG, Uvm

Jtag, Dft, ATPG, Scan Insertion

Scripting skills: Tcl, boundary scan , Vcs, System Verilog, Memory BIST, primetime, Logic Equivalency checking, Post-silicon validation and debug, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, EDA Tools, BIST architectures, Tessent tool sets, TestMax

Jtag, Shell, Python, Tcl, scan compression, IEEE 1149.x, automation infrastructure, automation and scripting, MBIST, DFT implementation methodology, IEEE 1687, DFT EDA tools, ATPG, Cad Methodology, hierarchical DFT methodologies, LBIST