C, Makefile, Windows, Perl, Linux, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools

Perl, Python, Dft, SV, coverage metrics, Profiling Tools, Uvm, X prop, constrained random testing

Debugging, occ, ICL, Dft, DRC coverage, pdl, Scan ATPG, Simulation, IJTAG, SSN

debug validation on automatic test equipment, Algorithmic Test Pattern Generation, fault modeling, silicon bring-up, ASIC DFT synthesis, Scan ATPG, MBIST, STA simulation and verification flow, DFT Design for Test technologies, DFT specification and definition, IP integration

logic bist , Jtag, PERL, Shell script, Python, E-fuse, Pattern Retargeting, BSDL, Pattern simulation, Post Silicon debug analysis, DFT architectures, IDDQ, Chip level DFT, Fault Models, ATPG Pattern generation, scan chain insertion and verification, SDC constructs for DFT modes, Digital design concepts, pattern generation for Memories, MBIST, Scan Compression Techniques, JTAG IJTAG, ATPG coverage analysis, Transition faults, stuck at, scan patterns and coverage statistics

Python, Perl, Dft, Uvm, SV, Profiling Tools, constrained random testing, coverage metrics

boundary scan , Static Timing analysis, Perl, SDF, Tcl, ATPG vectors, TDL for ATE, formal verification tools, DFT simulation, tap controller, P1500, characterization DC Characteristics, MBIST insertion, Scan coverage, DFT tools from Mentor, netlist-based insertion flows

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence