Scripting Languages, Sta, Synthesis, EMIR, PNR, debugging skills, Digital Implementation flow, Flow development

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure

static timing analysis, PVT conditions, timing budgeting, timing rollups, Timing Analysis, timing constraint adaptation, clock network optimization, timing models

redhawk , Perl, Python, Tcl, EMIR sign-off flows, Voltus, electromigration analysis, Totem, chip-package co-simulation, EMIR sign-off methodology, chip-package co-design, PDN planning, PDN architecture planning

hardware engineering , Perl Scripting, Sta, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design, PDN Methodology, PPA Targets, Timing Signoff

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

Verilog, Tcl, ASIC design flow, low-power techniques, DFT Design for Test, UPF Unified Power Format, primetime, Synopsys Design Compiler NXT DCnext, Fusion Compiler, Formality, systemverilog, MCMM flows

layout verification , System Verilog, Tcl, design rules, Vlsi Design