Debugging, Test architecture definition, Scan Insertion, Timing constraints for test mode timing closure, Scan and ATPG for different fault models, LEC checks, Zero delay and timing simulations, RTL changes for DFT, Post silicon bring up, DFT ownership, IEEE1687 iJTAG compliant ICL PDL for functional manufacturing tests, Boundary scan ACJTAG IEEE 1500 implementation and verification, Low power CLP checks

Pcie, Verilog, Ethernet, Synthesis, cdc, UALink, Simulation, timing considerations, UCIe, systemverilog, LINT, CXL

conformal lec , Clp, Perl, Python, Tcl, Fusion Compiler, Formality, LEC, MCMM methodologies, UPF, Cadence Genus, Synthesis, Synopsys Design Compiler, RTL-to-GDS, CPF, Low Power Verification

Java, C, Python, SIMD vectorization, Cache-aware execution, Performance profiling, Parallel execution strategies, qemu, Benchmarking, Optimization

static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Synthesis, multi-voltage design, floorplanning, SDC constraint development, MBIST, test specifications, Dfm, formal verification, Timing Closure, DRC, debug test coverage, Scan, ESD checks

bandgaps, capacitor matching, CMOS image sensors, Simulation, Cadence, noise analysis, Pll, Dft, bias op-amps, transistor level circuit design, top chip integration, Verification, LDOs, tapeout, AI tools, ADC architectures, analog mixed signal design, SERDES, switched-cap circuits, Timing Analysis, Silicon Bring up, feedback and compensation techniques, TCAD, high-speed TX, CMOS pixel design techniques