synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, jitter, path-based analysis, false paths, Timing Closure, AOCV, skew

Perl, Python, Tcl, LVS DRC violations, Timing area and power constraints, Block-level place and route, P R flow development, CAD and physical design methodologies, Clock network guidelines, Physical design verification, Logic equivalency RTL2Synthesis, Physical Design, Synthesis2APR netlist, PPA optimization

High-speed timing closure (~4GHz), Clock tree synthesis (CTS), DDR/HBM/UCIe IP implementation, Mixed-signal hard macro integration

static timing analysis, Sta, Synthesis, 3DIC integration, LIB, LVS, Place And Route, ASIC development, SoC integration flows, RTL2GDS flows, tapeouts, LEF, digital-top physical design, EMIR, Dft, DRC, EDA infrastructure

rc extraction , routing, Tempus, LVS, Cadence layout tools, Innovus, ERC, STA timing closure, DRC, Placement, Caliber tool, IR EM analysis, block level low power aware floorplanning, tape out activities, Clock Tree Synthesis

Static Timing Analysis, Routing, Scripting, Extraction, EM, Ir, Floor-plan Physical Implementation, Physical Design, primetime, Placement, Design Compiler, DRC, Power-plan Synthesis, LVS, Cadence Genus, Formal Equivalence, Physical Verification, CTS, Innovus, PNR tools, ICC2, Mentor Graphics Calibre, Synopsys Fusion Compiler, Crosstalk Analysis, Apache Redhawk, Timing Closure, RTL to GDS2 flow, StarRC

Perl, Tcl, Full-custom memory layout development, EDA Tools, ERC, EMIR analysis, DRC, LVS, Cadence Virtuoso

Caliber DRC, Virtuoso XL, ERC, cadence LVS, LVS verification and debugging tools, layout design and verification tools, rmap