He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes.
Timing closure above 4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job.
Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage.
Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality.
Who You Are:
Typically requires a minimum of 6+ years of related experience after the post graduation.
Possesses a full understanding of specialization area plus working knowledge of multiple related areas.
A team player Independently resolves a wide range of issues in creative ways on a regular basis.
Customarily exercises independent judgment in selecting methods and techniques to obtain solutions.
Performs in project leadership role. Contributes to complex aspects of a project.
Determines and develops approach to solutions.
Work is independent and collaborative in nature.
Provides regular updates to manager on project status.
Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.
