Search by job, company or skills

Ayar Labs

Director, ASIC Physical Design

Ayar Labs
Bengaluru, India
12-14 Years
Save
new job description bg glownew job description bg glow
  • Posted 2 days ago
  • Be among the first 10 applicants
Early Applicant

Job Description

Location: Bengaluru (on-site, flexible hours)

Ayar Labs is seeking a Director of ASIC Physical Design to develop and tape out the next generation of electronic-photonic integrated chips. The candidate will be responsible for leading the ASIC integration team, performing design integration, physical design, and tapeouts of ICs containing custom analog, photonic, and digital subsystems implemented in both 3DIC and specialty platforms. The ideal candidate will be a mission-driven team leader with management and leadership experience in product-focused organizations, with a comprehensive silicon development background, a track record of first-silicon successes, and eagerness to apply specialized ASIC skillsets to a wide range of problems.

Essential Functions

  • Manage and grow the skillsets of an experienced ASIC integration team which has successfully taped out multiple generations of Ayar Labs SoCs
  • Drive timely execution of both test chip and product tapeouts
  • Develop and improve upon complex SoC integration flows integrating photonics, circuits, advanced nodes, and 3DIC integration in leading edge nodes
  • Oversee digital-top physical design and RTL2GDS flows: synthesis, place and route, and static timing analysis
  • Drive clear and effective decision-making across multiple functions and teams within the organization
  • Implement SoC signoff and cross-check methodologies to deliver high-quality tapeouts incorporating a wide range of disciplines
  • Maintain EDA infrastructure for the broader design organization

Basic Qualifications

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related fields
  • 12+ years of experience in ASIC development and tapeouts
  • 5+ years of Experience leading teams of both local and remote engineers through successful tapeouts in multiple leading edge technologies
  • Experience driving tool and IP vendor evaluation and selection
  • Strong problem solving skills and demonstrated ability to apply known methodologies towards new problems
  • Expert in a broad set of ASIC flows and methodologies: RTL2GDS, EMIR, DFT, STA, LVS, DRC, LIB/LEF
  • Experience working with integration of analog and digital components into SoC's
  • Passionate about developing and enhancing build flows, methodologies, and automation
  • Strong communicator and team-builder who can drive cross-functional alignment

Preferred Qualifications

  • Experience with design or implementation of SerDes IP block interfaces in a complex SoC fabric environment
  • Core knowledge of semiconductor physics
  • Working knowledge of optics and silicon photonics

Note To Recruiters

Principals only. We are not accepting resumes from recruiters for this position. Remuneration for recruiting activities is only applicable subject to a signed and executed agreement between the parties. Please don't send candidates to Ayar Labs, and do not contact our managers.

More Info

Job Type:
Permanent Job
Industry:
Other
Function:
Semiconductors
Employment Type:
Full time

About Company

Ayar Labs

Job ID: 148441425

Jobs by Skill - IT
Jobs by Skill - Non IT
International Jobs
Last Updated: 28-05-2026 05:18:17 PM
Homejobs in Bengaluru / BangaloreDirector, ASIC Physical Design

Similar Jobs

Principal Engineer, ASIC Physical Design

Ayar Labs
Bengaluru, India

Skills:

static timing analysis, Python, Verilog RTL, Genus Design Compiler, scripting or programming languages, DFT methodologies, high-speed SerDes, ASIC synthesis, Asic Physical Design, physical verification DRC LVS, 3DIC implementation methodologies, Cadence Virtuoso, RTL Compiler, place-and-route Encounter Innovus ICC, Clock Tree Synthesis

ASIC Physical design Engineer

AMD Telecom
Bengaluru, India

Skills:

Scripting, Static Timing Analysis, Routing, Design Compiler, CTS, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, RTL to GDS2 flow, Floor-plan Physical Implementation, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

ASIC Physical Design Lead

Advanced Micro Devices (AMD)
Bengaluru

Skills:

Rtl Design, Physical Verification, DPT Optimization, Timing Closure, Place And Route

Director, Engineering IT

Marvell Technology - Multimedia Solutions Business
Bengaluru, India

Skills:

AWS, Networking, Itil, Azure, Servicenow, Gcp, hybrid infrastructure models, Synopsys, HPC environments, Siemens EDA, EDA Tools, cloud platforms, compute storage grid, Cadence, Scheduling, SRE practices

Director, HW Design (AI2440)

SiMa.ai
Bengaluru, India

Skills:

static timing analysis, Verilog, Synthesis, SoC integration, design constraints, embedded CPUs, IP integration, systemverilog, Rtl Design, ML AI accelerators, Axi, BUS Protocols, clock power reset domains, low-power design techniques, AHB