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Job ID: 147238779
Skills:
C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, automating workflows in a distributed compute environment, developing UVM based verification frameworks, simulation profile efficiency improvement, TLM, debugging firmware and RTL code using simulation tools
Skills:
Vcs, JIRA, Git, Bitbucket, Perl, Verilog, Python, Tcl, CVS, Gate-Level Simulation, Xcelium, Palladium, Uvm, systemverilog, Assertions, Zebu, Protium, Questa, RTL-to-Gate-Level Simulation, HAPS, SoC Verification
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