Memory IP (DDR/HBM/GDDR), Test Planning, Debugging, Design Verification, systemverilog, Uvm, Vlsi, Verification Environment Development, Functional Verification

code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

testbench development, UVM methodology, test plan reviews, debugging complex IP designs, systemverilog