Sr Principal Design Engineer

Key Responsibilities

• Lead and execute functional verification of complex VLSI/IP designs from concept to verification closure
• Develop verification environments using SystemVerilog and UVM methodology
• Create detailed test plans and drive environment planning for verification projects
• Design, implement, and maintain reusable UVM-based verification components
• Perform functional verification of complex designs ensuring coverage closure and quality metrics
• Collaborate with design teams to define verification strategies and requirements
• Debug functional issues using simulation tools and waveform analysis
• Ensure adherence to verification best practices and improve existing methodologies
• Drive verification closure for IP/subsystem-level projects