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Showing 8 jobs
Skills:
System Verilog, Building test benches from scratch, ASIC verification using UVM
Skills:
C, System Verilog, Scripting, digital design fundamentals, post Silicon validation, computer organization architectures, AMs, Uvm, BUS Protocols, Simulation, Low Power Verification, formal verification
Skills:
code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage
Skills:
Unix, Unix Shell Scripts, Perl, Python, make, Uvm, systemverilog
Skills:
Python Scripting, Jasper, Verilog, System Verilog, formal verification, VC-FORMAL, SVA
Skills:
Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog
Skills:
Tcp, Pcie, Ethernet, System Verilog, RDMA, Building test benches, Data path verification performance tests, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification
Skills:
Python, Systemc, MDV, simulation scripts, hybrid testbenches, regression systems, verification execution, Uvm, systemverilog, testbenches, CDV, coverage models
