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Job ID: 148444925
Skills:
code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage
Skills:
Ovm, Verilog, System Verilog, DFI protocol, formal verification, Jedec standards, Functional Verification Coverage, Design Verification, Uvm, Low Power Verification, Gate Simulation
Skills:
python, perl, System Verilog, Computer Architecture, Network on Chip verification, Configurable IP verification, coherency architecture, AMBA protocols, VIP integration, coherent protocols, bridge checkers, protocol checkers
Skills:
Fpga, Perl, Python, RTL, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, low power verification methods, object-oriented design, formal verification methods, transaction level modeling, test plan development, emulation platforms
Skills:
System Verilog, Data path verification performance tests, Building test benches from scratch, Gate level simulation, ASIC verification using UVM
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