Synthesis, Design Compiler, primetime, SDC timing constraints, STA timing closure, Genus, ASIC tapeout, Tempus, systemverilog

static timing analysis, Verilog, Synthesis, Design Reviews, SoC debug architecture, SoC integration, DFT concepts, formal verification tools, ARM coresight components, systemverilog, Rtl Design, Simulators, formal verification, constraints timing analysis, Optimization Techniques, Verification, APB protocol