code coverage , perl, C, Regression Testing, Ovm, Pcie, Ethernet, Python, Uvm, systemverilog, Axi, DDR protocols, RTL simulators, X-propagation, functional coverage

Unix, Unix Shell Scripts, Perl, Python, make, Uvm, systemverilog

Jtag, Perl, Verilog, Python, System Verilog, Tcl, Mentor Questa, Cadence Xcelium, JasperGold, Uvm, Synopsys VCS, APB, EDA Tools, CRI, IJTAG

Vcs, DDR, Shell, Pcie, Perl, Ethernet, Python, Verdi, CHI, IUS, Uvm, systemverilog, Axi, Questa, AHB

Automation Frameworks, Ovm, Cadence Palladium, Mentor Veloce, verification methodologies, emulation tools, emulation platforms, Uvm

Mac, Pcie, Switches, Ethernet, FPGA verification, RDMA, NICs, SmartNICs, networking architectures, Uvm, systemverilog

bandwidth management , Microprocessor Cores, Specman E, hierarchical memory subsystems, Debug, interconnects, IP subsystem SoCs, congestion control, systemverilog, constrained-random verification, packet processing, Verification, standard IP components