Perl, Verilog, Shell Scripting, LINT, cdc, RTL Quality Checks, Micro Architecture Definition, Connectivity, SOC design, VCLP

Rtl Design, Subsystem design, Axi, APB, SoC integration, Subsystem IP integration, Microarchitecture

Python Scripting, ASIC design flow, Circuit timing STA, C embedded experience, Digital Design, Low power digital design and analysis, RTL design in Verilog SystemVerilog, ASIC design in sub-20nm technology nodes, PrimeTime or equivalent tools

LINT, Sta, Synchronous design concepts, Memory operation, power analysis, SoC design flows, CMOS Circuit Design, Rtl Design, Synthesis, spyglass, device physics, CDC methodologies

Shell, Tcl, Perl, DMA, digital design fundamentals, control data path logic, protocol bridges, low-power design flows, systemverilog, power performance and area optimization techniques, lint CDC RDC synthesis STA constraints, RTL design using Verilog, memory-mapped peripherals, micro-architecture definition, Dft, bus fabrics, debugging skills for simulation synthesis and integration issues

memory controllers , Verilog, Flash, Ddr3, Sta, CHI, Memory, clocking system modes, Rtl Design, Security, physically aware design flows, power management, LPDDR, Bunch-of-wires, Synthesis, multi-clock domain architectures, power optimization techniques, Debug, D2D protocols, UCIe, systemverilog, Rom, Axi, Timing Closure, low-power design techniques, AHB, Ram

Rtl Design, Subsystem design, Axi, SoC integration, APB, Subsystem IP integration, Microarchitecture