Tcl Scripting, EDA timing tool competence, primetime, spyglass, Tweaker, SDC knowledge, Fishtail, Synopsys Design Compiler, DMSA

Sta, LINT, Synthesis, cdc, Dft, MMMC, primetime, Tempus, SDF generation, ETM Timing model generation

Timing Concepts, low-power design and multi-voltage domains, STA tools like Synopsys PrimeTime, synthesis and place route flows

monte carlo , Perl, Python, Tcl, FineSim, Hspice, PT Tempus, Spice, Layout Parasitic Extraction, Signal Integrity, ICC, digital flow design, primetime, Innovus, ASIC back-end design flows, STA setup, Timing Analysis

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew

synopsys primetime , Tcl, Python, Perl, Cadence Tempus

synopsys primetime , Static Timing Analysis, AOCV, Clock tree concepts, ASIC design flow, Cadence Tempus, POCV methodologies, SDC constraints, MCMM timing analysis, OCV

RTL2GDS, STA convergence, Synopsys, EDA Tools, Physical Design, Synopsis Primetime, Cadence