STA Engineer

JD for STA - 5+ yrs, bangalore, coimbatore

STA - 5+yrs

CTC: yoe*4x

Role Overview

We are seeking an experienced STA Engineer with 5+ years of hands-on experience in ASIC/SoC timing analysis and closure. The candidate will be responsible for performing block-level and full-chip timing analysis, debugging timing violations, and ensuring designs meet timing requirements across multiple corners and modes.

Key Responsibilities

Static Timing Analysis

• Perform block-level and full-chip STA for ASIC/SoC designs.
• Analyze and fix setup, hold, recovery, and removal timing violations.
• Perform timing sign-off across multiple PVT corners and modes (MCMM).
  
  

Timing Closure

• Work closely with RTL, synthesis, and physical design teams to achieve timing closure.
• Analyze critical paths, clock paths, and false paths.
• Provide recommendations for timing optimization and ECO implementation.
  
  

Sign-Off and Verification

• Perform timing sign-off checks using industry-standard EDA tools.
• Validate timing with OCV/AOCV/POCV methodologies.
• Review constraints such as SDC and timing exceptions.
  
  

Debug & Analysis

• Investigate timing violations and root-cause issues.
• Work with cross-functional teams to fix timing problems at design and physical levels.
• Support silicon bring-up and timing correlation when required.
  
  

Required Skills

• 5+ years of experience in Static Timing Analysis
• Strong understanding of ASIC design flow
• Experience with timing analysis tools such as:
• Synopsys PrimeTime
• Cadence Tempus
• Strong knowledge of:
• SDC constraints
• Clock tree concepts
• MCMM timing analysis
• OCV/AOCV/POCV methodologies