Usb, Pcie, Perl, Verilog, Shell scripting, Python, systemverilog, Axi, VHDL, Formal Verification Flow, APB, Cadence JasperGold, AHB

Shell, Python, Perl, complexity reduction techniques, formal verification technologies, high quality testplans, formal testbenches

Python, Low Power Formal Methodology, Jasper VC Formal, formal verification, Formal Tools, Property-based FV, SVA, Questa Formal

Tcl, Perl, JasperGold, digital design concepts, Questa, VC Formal, systemverilog, debugging complex design bugs, convergence techniques, formal coverage metrics, RTL coding in Verilog, Formal OneSpin, formal verification, formal property specification

Python., Verification methodologies, formal verification tools, Uvm, systemverilog

Python, IBM Formal verification tools, Formal Functional Verification