Static Timing Analysis, Python, Logic Design, Jasper, Perl, Tcl, Sta, IR drop, RTL implementation, post silicon validation, DFT concepts, Cadence Modus, Verification, Synthesis, ATPG tools, coverage analysis, Scan Insertion, RTL2GDS flow, Logic Synthesis, debugging skills, RTL lint tools, ATE debug, Logic Equivalent Checking, EDA Tools

logic bist , static timing analysis, UNIX, Jtag, Linux, Verilog, Synthesis, DFT techniques, Scan Insertion, memory BIST, equivalency checking, ATPG, EDA Tools, scan compression architecture, IEEE standards, SSN Scan

logic bist , static timing analysis, UNIX, Jtag, Perl, Linux, Verilog, Tcl, DFT techniques, Synthesis, Scan Insertion, memory BIST, waveform debugging tools, equivalency checking, ATPG, EDA Tools, scan compression architecture, SSN Scan, IEEE standards, c-shell

Jtag, Adaptive, DFT architectures, XOR

logic bist , boundary scan , simulation and verification flow, clock control block, DFT compression, silicon debug, DFT technologies, scan chains, fault modeling, DFT strategy and architecture, IP integration, DFT specification definition, DFT design and verification, DFT architecture, die level DFT validation, silicon bring-up, ASIC DFT synthesis, TAP controller

Jtag, Dft, MBIST, Design Engineer

Understanding of low-power design flows, ATPG and test coverage analysis using industry standard tools, Gate level simulation using Synopsys VCS and Verdi, Knowledge of fault models, JTAG Scan Compression and ASST implementation, Fluent in RTL coding for DFx logic, Exposure to post-silicon testing and tester pattern debug, Familiarity with SystemVerilog and UVM, Understanding of DFT Architectures and micro-architectures, MBIST planning implementation and verification