Job description
5+ years to 10 yrs design experience
- Experience with owning chip level DFT and Post Silicon debug / analysis
- Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification.
- Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories(E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation.
- Understanding generation of functional patterns for ATE
- Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc)
- Design experience in MBIST / LBIST is an added advantage.
- Good understanding of constraints development for physical design implementation/static timing analysis.
