code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

Scripting, Automotive FuSa, debug skills, GCM protocol, AI-assisted design tools, AES Encryption Decryption algorithm, Design Tools, PCIe design

C, System Verilog, Python, Synthesis, Behavioral coding, Synthesis and SDC Creation, low power design, Debugging verification test cases, Digital architecture, Design Architecture, Design implementation, Synthesis constraint generation, Low-power designs, Digital RTL, Scripting of design automation, power management, Embedded uC Designs, Timing Analysis, Dft, uC Based subsystems