low power design, LINT, cdc, Charging voltage regulation, Interconnect fabrics, Clock domain crossing, Battery management, Familiarity with Cadence Synopsis design tools, Synthesis, Verilog Coding, RDC, Serial interfaces, Register file design, Power intent specification and validation methodology, RTL Coding, Microarchitecture Module design and simulation, Scan and self-test, State machine architecture, Knowledge of TFM Tools Flows and Methodologies, ARM based Subsystems SOCs, Verification including System Verilog knowledge, Synthesis Linting STA, Simulation, Automation scripting and design flows, Digital design implementation and integration

Synthesis constraints, RDC violations, RTL linting, RTL integration, AHB protocol, Architecture micro-architecture development, Timing Closure, SoC components, Clocking and reset concepts, RTL Coding, Network on chip, Debug and error warning fixes using VcSpyglass, Timing paths

static timing analysis, Verilog, Synthesis, Design Reviews, SoC debug architecture, SoC integration, DFT concepts, formal verification tools, ARM coresight components, systemverilog, Rtl Design, Simulators, formal verification, constraints timing analysis, Optimization Techniques, Verification, APB protocol