Ecos, Python, Tcl, physical closure, CTS, Fusion Compiler, ICC2, physical design implementation, Asic Physical Design, Timing Concepts, Innovus, PD flows and methodologies

Synopsys tool suite, physical design verification, IR EM analysis and resolution, ICV or Calibre tools, block level and full-chip physical verification methodology, full chip floor-planning and integration, complete physical design flow, block subsystem timing closure

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

redhawk , Ecos, floorplanning, low-power design methodologies, Tempus, Physical Verification, Voltus, Innovus, Physical Design, Genus, IR drop analysis, GDSII

Unix, Perl, Verilog, System Verilog, Python, Tcl, Synopsys Fusion Compiler, PPA tradeoffs, Power Planning, Physical Design, Timing Closure, Innovus, Timing Power EM IR PDV

Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route

Static Timing Analysis, Fusion Compiler, Physical Design Flow, floorplanning, ICC2, Innovus, primetime, Synthesis, Power Rail Grid Design, Mentor Graphics, Place And Route, Clock Tree Synthesis

Perl, Verilog, Python, Tcl, CTS, Post-Route Optimization, Synthesis, VHDL, Placement, CDNS, SNPS, P and R tools