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Physical Design Engineer
Job Summary
The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.
Key Responsibilities
Required Qualifications and Skills
Education
Technical Skills & Experience
Soft Skills
Experience Level :- 5yrs to 10yrs
Notice Period :- Immediate to 30 Days
Work Location :- Bangalore
Mode of Work :- WFO
Employment Type :- Permanent
Job ID: 147322215
Skills:
NDM Liberty .lib, Scripting, Timing Model Deliverables, AI-driven Automation, Physical Design, LibBuilder Flow, Library Management, AI-assisted Tools, MemView Generation, PVT Corner Coverage, LEF
Skills:
Routing, DDR design knowledge, floorplanning, Calibre, primetime, Innovus, RTL-to-GDSII implementation, Placement, EDA Tools, Genus, Tcl tool scripting, Physical Design Methodologies, MultiTap-CTS
Skills:
redhawk , Synopsys ICC2, PNR and signoff tools, Cadence Innovus, Physical Verification, IR EM mitigation, PDN methodology, floorplanning, STA constraints, physical design implementation, primetime, Tempus, Voltus
Skills:
Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Signal Integrity, Leakage Power, Multi-Vt Flow, Dfm, IC design, Power Supply Management, Deep Sub-Micron Design Problems, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff
Skills:
power optimization , routing, Perl, Verilog, Python, Tcl, Synthesis, submicron process node technologies, Timing Analysis, power delivery methodologies, LVS, Power Estimation, formal verification, VHDL, layout verification methods, DRC, Placement, low-power design techniques, timing signoff, Clock Tree Synthesis