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Physical Design Engineer
Job Summary
The Physical Design Engineer will be responsible for the full-chip and/or block-level physical implementation of complex digital, mixed-signal, or RF integrated circuits from RTL to GDSII (the final manufacturing data). This role requires expertise in design methodologies to achieve optimal performance, power, and area (PPA) targets while ensuring manufacturability.
Key Responsibilities
Required Qualifications and Skills
Education
Technical Skills & Experience
Soft Skills
Experience Level :- 5yrs to 10yrs
Notice Period :- Immediate to 30 Days
Work Location :- Bangalore
Mode of Work :- WFO
Employment Type :- Permanent
Job ID: 147322215
Skills:
power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2
Skills:
routing, Scripting Languages, Python, Perl, Tcl, power analysis, primetime, Fusion Compiler, Cadence Innovus, DFT insertion, manufacturing sign-off, Voltus, EDA Tools, low-power design, EM IR analysis, sign-off, advanced nodes, multi-clock domain handling, Synthesis, floorplanning, ASIC SoC physical design flows, Timing Analysis, Physical Verification, reliability checks, Signal Integrity, Timing Closure, Placement, Synopsys ICC2, Clock Tree Synthesis
Skills:
Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route
Skills:
Perl, Verilog, Python, Tcl, CTS, Post-Route Optimization, Synthesis, VHDL, Placement, CDNS, SNPS, P and R tools
Skills:
Tcl Scripting, Static timing Analysis, Cadence Tools, Synthesis, Physical Design, Physical Verification, Backend flows, Clock Tree Synthesis, Place Route Reliability
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