PERL, Python, Tcl, Synthesis, Cadence

synopsys tools , static timing analysis, constraint development, power-saving strategies, timing methodologies

Sta, LINT, Synthesis, cdc, Dft, MMMC, primetime, Tempus, SDF generation, ETM Timing model generation

synopsys primetime , Debugging, Python, Perl, Tcl, OCV, timing closure techniques, latency, multicycle paths, derates, MMMC concepts, SDC timing exceptions, timing constraints development, POCV, ECO methodologies, clock uncertainty, Case Analysis, setup hold analysis, Cadence Tempus, clock tree, path-based analysis, jitter, false paths, Timing Closure, AOCV, skew

Timing Concepts, low-power design and multi-voltage domains, STA tools like Synopsys PrimeTime, synthesis and place route flows

Sta, RTL2GDS, physical design EDA tools, Cadence, Synopsys, Synopsis Primetime

Python, Tcl, Cadence Innovus, Logic Synthesis, Setup Hold analysis, Cadence Genus, Cadence Tempus