Senior STA Engineer

Responsibilities:

Exp: 5 -8 Years

• Lead and develop timing methodologies, establish SDC constraints, and automate processes for special timing checks, ensuring design convergence and managing ECOs effectively.
• Proficiency in performing static timing analysis (sign-off) for multi-corner, multi-voltage processes to align with PPA targets, at both block level and chip level, reviewing the timing arcs for the .lib generation.
• Be responsible for constraint development, validation at the block/subsystem/full chip level.
• Collaborate closely with Business Units and EDA vendors to ensure quality enhancements and address flow concerns thus enabling cutting edge signoff methodology.
• Implement power-saving strategies, such as power gating, multi-voltage domains, and clock gating, to meet low-power objectives while preserving performance standards.
• Create and refine custom scripts using Python, Tcl or Perl to enhance workflow efficiency and streamline Signoff design operations.
• Mentor and support junior design engineers, disseminating best practices and providing technical guidance to elevate team proficiency and performance.

Desired Skills:

• Proven ability in timing analysis, convergence, timing ECOs, and .lib generation on advanced technologies.
• Proficient in industry standard Static Timing Analysis tools using Cadence or Synopsys toolsets
• Understanding the timing requirements across Digital and Analog interfaces is a plus
• Excellent problem-solving, leadership, and communication skills and values team culture.
• Capable of thriving in fast-paced environments and good at multi-tasking.