Static Timing Analysis, Fusion Compiler, Physical Design Flow, floorplanning, ICC2, Innovus, primetime, Synthesis, Power Rail Grid Design, Mentor Graphics, Place And Route, Clock Tree Synthesis

Perl Scripting, Sta, High Speed Cores, Circuit Level Comprehension, RTL to GDSII Implementation, Leakage Power, Signal Integrity, Multi-Vt Flow, IC design, Dfm, Power Supply Management, Deep Sub-Micron Design, Physical Design, Power Gating, High Frequency Design Convergence, PDN Methodology, PPA Targets, Timing Signoff

Unix, Perl, Verilog, System Verilog, Python, Tcl, Synopsys Fusion Compiler, PPA tradeoffs, Power Planning, Physical Design, Timing Closure, Innovus, Timing Power EM IR PDV

Perl, Verilog, Python, Tcl, CTS, Post-Route Optimization, Synthesis, VHDL, Placement, CDNS, SNPS, P and R tools

Scripting, Static Timing Analysis, Routing, Design Compiler, primetime, ICC2, Synopsys Fusion Compiler, LVS, Cadence Genus, Innovus, Physical Verification, Extraction, Formal Equivalence, StarRC, Placement, Floor-plan Physical Implementation, RTL to GDS2 flow, Power-plan Synthesis, Apache Redhawk, Mentor Graphics Calibre, Crosstalk Analysis, EM, Ir, Physical Design, Timing Closure, DRC, PNR tools

Scripting, PERL, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, RTL2GDSII flow, ICC2, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, Timing Closure, High Frequency Design Methodologies, Place And Route

cadence encounter , Unix, Shell, Linux, Flow automation, Synopsys ICC2 tool set, Physical Design, SDC STA, Python Script, PnR tools like ICC2 Innovus, Equivalence checking, Skill

Tcl Scripting, Static timing Analysis, Cadence Tools, Synthesis, Physical Design, Physical Verification, Backend flows, Clock Tree Synthesis, Place Route Reliability

Cadence Innovus, Netlist to GDSII flow, Synopsys ICC