PERL, Skill, Cadence LVS, memory architectures, LVS, Cadence Virtuoso layout editor, ERC, optimized layout design, DRC, Calibre physical verification flow, Finfet technology, layout design and verification tools

Machine Operating, Processing Problems, Developing, Hydraulics Circuits, Service Portal, Business Development

OEM fluid and pneumatic components, Fmea, Plastic materials

power optimization , low power design, Technical Specifications, Verification Test plan reviews, Micro-architecture requirements, Data Fabric NoC features, Power management microarchitecture

Gcp, Azure, AWS, oci, Troubleshooting

C, Debugging, Python, OTDR, embedded environments, optical control loops, ROADM, Amplifiers, Troubleshooting, DGE, Raman

Tcl, Bash, Python, Perl, Sound Forge, Microsoft Word, multimedia authoring tools, testbench creation, Simulation, UVM methodology, systemverilog, Adobe Acrobat, Microsoft Powerpoint, camtasia, HDL design, Verification, Debug

Physical Verification, Physical Design, floorplanning, Timing Closure, SoCs, Package Co-design, Place And Route, Clock Tree Synthesis, IO Planning, Power Grid Design