Makefile, Windows, Perl, Linux, Python, IP-level ASIC verification, simulation profiling, UVM methodology, UVM testbenches, systemverilog, formal verification, UVM-based verification frameworks

PERL, Verilog, Tcl, Uvm, systemverilog

IP-level ASIC verification, Linux and Windows environments, UVM methodology, Efficiency Improvement, UVM testbenches, Simulation profiling, systemverilog, formal verification, UVM-based verification frameworks

Usb, DDR, Pcie, Verilog, UVM based Verification IP development, Scripting for automation, Uvm, systemverilog, AMBA AXI, APB, AHB, System Verilog Assertions

C/C++, systemverilog, modern verification libraries, Uvm, penGL/OpenCL/D3D

Vcs, RTL implementation, formal verification, Mentor Graphics, Cadence, Uvm, systemverilog