Design Verification Engineer
Design Verification Engineer
MosChip SemiconductorThis job is no longer accepting applications
Job Description
Responsibilities
Understand the standards/specifications
Architecture development and documenting implementation level details
Hands on work for every aspect of verification cycle
Responsible for the compliance with the latest Methodologies.
Developing Verification IPs
Define Functional Coverage matrix and Comprehensive Test plan
Regression management and functional coverage closure
DUT integration and verification for IP delivery sign-off
Leading small team
Person Specification
Required Skills
Hands-on experience of complete verification cycle with strong verification concepts
Strong knowledge of Verilog, SystemVerilog and UVM
Experience in UVM based Verification IP development
Experience in AMBA AXI/AHB/APB System buses
Hands on work experience on any of PCIe/Eth/USB/DDR etc.
Hands on experience with System Verilog Assertions
Scripting for automation, release process, simulations, regressions
Good command over written and oral communication
Desirable Skills
DV Engineer, Design Verification, Verification Engineer
Understand the standards/specifications
Architecture development and documenting implementation level details
Hands on work for every aspect of verification cycle
Responsible for the compliance with the latest Methodologies.
Developing Verification IPs
Define Functional Coverage matrix and Comprehensive Test plan
Regression management and functional coverage closure
DUT integration and verification for IP delivery sign-off
Leading small team
Person Specification
Required Skills
Hands-on experience of complete verification cycle with strong verification concepts
Strong knowledge of Verilog, SystemVerilog and UVM
Experience in UVM based Verification IP development
Experience in AMBA AXI/AHB/APB System buses
Hands on work experience on any of PCIe/Eth/USB/DDR etc.
Hands on experience with System Verilog Assertions
Scripting for automation, release process, simulations, regressions
Good command over written and oral communication
Desirable Skills
- Lead the Verification IP development with 2 or more junior engineers
- Exposure to full verification cycle
DV Engineer, Design Verification, Verification Engineer
More Info
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Key Skills
About Company
Skills:
C, Makefile, Windows, Shell, Linux, Perl, Verilog, Ruby, System Verilog, Systemc, IP level ASIC verification, graphics pipeline knowledge, HLS tools, UVM testbenches, simulation profile efficiency improvement, UVM based verification frameworks, TLM, debugging firmware and RTL code using simulation tools
Skills:
C, Debugging, Verilog RTL, Verification Techniques, Communication Interfaces, Scripting and Automation, EDA Tools, Uvm, Digital and SoC Verification, C DPI, systemverilog
Skills:
SoC Verification, Uvm, Debugging Expertise, Verification Planning, C DPI Development, Scripting and Automation, systemverilog, Coverage-Driven Verification