Calibre, Analog Layout, Cadence Virtuoso XL, Design for Manufacturability Principles, Signal Integrity Analysis, Power Distribution Techniques

Verification Tools, scripting expertise, Cadence LVS, layout XL, Calibre physical verification, EXL, Cadence Virtuoso, GXL

fast simulation tools and waveform viewers, deep submicron technology challenges, NMDL and CCST libraries, writing SPICE decks stimulus and test vectors, FinFET technology, layout impact on speed capacitance power and area, generating libraries and performing QA sign-off, layout parasitic extraction, memory architectures and performance optimization, LVS DRC debugging skills and verification for lower technology nodes, memory leafcell layout design, EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse

PERL, Python, Tcl, Ir, Cadence, Mentor, LVS, EM Signoff, Synthesis, Formal Equivalence, DRC, Synopsys

Unix, Linux, Perl, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

Shell, Perl, Ansys, Python, Tcl, EDA Tools, Cadence Skill, Mentor, Cadence Virtuoso, Cadence Synopsys

Perl, Unix Shell, Python, Tcl, IC Validator, Calibre, PERC, DRC, LVS, Cadence Virtuoso

DRC LVS-clean layouts, industry-standard layout tools, advanced technology nodes, physical verification and sign-off flows, memory layout design