Vcs, Bash, Perl, Verilog, X86, Arm, Python, Tcl, LINT, Design Compiler DC, cdc, CHI, Ace, Xcelium, RISC-V, AMBA protocols, systemverilog, Cadence Genus, Synopsys SpyGlass, Axi, VHDL, APB, AHB

Perl, Python, Tcl, asynchronous logic, state machines, digital design fundamentals, synchronous logic, systemverilog

Verilog, MIPI, FPD-Link, synthesis tools, DFT methodologies, Ethernet MAC PHY, systemverilog, SerDes digital architectures, high-speed digital design

Verilog, Debugging Tools, systemverilog, Rtl Design, Synthesis, FPGA Prototyping, Timing Closure, Verification Methodologies, low power design, Physical Design

Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Logic Design, Verilog, Microprocessors, low power design, LINT, cdc, Design Compiler, Memory controller designs, AMBA protocols, ASIC RTL Design, primetime, Synthesis, Axi, Asynchronous interface, APB, timing concepts for ASIC, RTL Coding, micro-architecture, Multi Clock designs, AHB, System-Verilog

Perl, Shell scripting, Python, Sta, SDC constraints, RTL design using Verilog, ASIC SoC development, Timing Analysis, systemverilog, digital design concepts, VHDL, Functional Verification, RTL debugging, UVM-based verification environments, Timing Closure, synthesis flows

FPGA Design, Perl, Verilog, Python, systemverilog, Synthesis Checks, Digital Design, Custom IP Development

Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design