PYTHON, PERL, Scripting Languages, Tcl, Scan-DRC tk methodology, Fusion compiler, PnR tools, low power methodologies, FV CLP, PD ownership, PDN STA, LEC low-power checks, ASIC designs, PDN STA closure, Innovus, CTS issues, Sign-off PV, HM level PV, debugging Congestion, Place and Route flow, Voltage Islands

PERL, Python, Tcl, Sta, CTS, Full-chip Floor-planning, Timing Convergence, ICC2, RTL2GDSII flow, Ir, Tempus, primetime, Innovus, Physical Verification, Synthesis, Layout Closure, Physical Design, High Frequency Design Methodologies, Seahawk, Place And Route, ECO Timing Closure

primetime, Fusion Compiler, low-power methodologies, Tempus, Cadence Innovus, Timing Analysis, Synopsys ICC2, EDA tool automation, ECO flows

cadence encounter , Unix Linux, Tapeout sign-off experience, SKILL Shell, Synopsys ICC2 tool set, Flow automation, 14nm 10nm 7nm 5nm process nodes, Python Script, PnR tools like ICC2 Innovus, SDC STA and Equivalence checking, Block SoC level Physical Design

Cadence PD Flow, Calibre, Innovus PnR, Quantus Extraction, Tempus STA, Voltus IR EM

Place Route CTS, Synthesis-to-signoff physical design flow, Physical Design, Timing convergence and closure techniques, IR EM analysis and power integrity checks, Cadence Innovus, Signoff DRC LVS

, Tcl, Perl, Fc, Routing, Python, Scripting, Synthesis, LEC, EDA Tools, Calibre, floorplanning, EMIR, ICV, Tempus, Placement, ERC, DRC, Power Planning, Genus, power analysis, Dc, LVS, Pt, pegasus, Physical Verification, Innovus, ICC2, formal verification