Verilog, Ethernet, System Verilog, RTL Coding, high speed protocols, System Verilog assertions, scripting in Perl

cdc, RTL Coding, Synthesis, Rtl Design, DV debug, Debug, Dft, ip design

Spi, Uart, Verilog, Arm, System Verilog, I2c, Gpio, USB standards, Synopsys, ASIC design flow, Interconnect fabrics, Arteris fabrics, RTL Coding, Cadence, Scripting in Perl, Peripheral interface IPs, QSPI, I3C, System Verilog assertions, NoC architecture, Third-party IP integration, Axi

Verilog, Sta, Synthesis, cdc, Dft, ATPG, RTL Coding, LINT, SDC creation, systemverilog

System Verilog, Pcie, CXL, RTL coding Verilog, AMBA controller IP, FPGAs

pipelining , Debugging, Perl, Verilog, Python, Tcl, Analytical Skills, Reset architecture, Clock domain crossing CDC, Micro-Architecture, Linting, Digital Design Fundamentals, systemverilog, FSM design, Synthesis, RTL quality checks, RTL Coding, Low-power design methodologies, ASIC SOC design, Timing Concepts

Coding, Usb, Verilog, Ethernet, Pcie, Sata, Rtl Design, RTL, ASIC Design, Principal