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Cadence Design Systems

Sr Principal RTL Design Engineer

12-20 Years
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Job Description

  • 12+ years of experience in ASIC design
  • Proficient in Verilog coding, RTL design and complex control path and data path designs
  • Knowledge of any of the interface Protocols like UCIe, PCIe, USB, MIPI(DPHY), HDMI/Display, Ethernet, SATA
  • Knowledge of RTL checks ex- LINT, SDC, CDC Familiar with synthesis flow, LEC and timing constraints
  • Experience in writing Verilog testbench and running simulations.

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Open to candidates from:
Indian

About Company

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality. For six years in a row, Fortune Magazine has named Cadence one of the 100 Best Companies to Work For. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health. We pride ourselves on creating and sustaining a company culture, that drives innovation and business success. Cadence is recognized as a Great Place to Work around the world, including as one of the Fortune “100 Best Companies to Work For” over the last six years.

Job ID: 115752207

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