routing, Perl, Python, Tcl, power analysis, voltage islands, EM Analysis, power gating, physical design methodology, power rail PDN analysis, noise analysis, Logic Synthesis, current density check, Placement, power integrity concepts, Clock Tree Synthesis

redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques

synopsys primetime , Scripting, Shell, Perl, Python, Tcl, Siemens Calibre, IR drop, Fusion Compiler, Cadence Tools, Power Reliability, ICC2, Tempus, LVS, Innovus, Physical Verification, Timing Analysis, ERC, Physical Design Tools, Synopsys Design Compiler, Genus, DRC, EM noise analysis

Scripting Languages, Sta, Synthesis, EMIR, PNR, debugging skills, Digital Implementation flow, Flow development

rc extraction , Ecos, Perl, Tcl, Sta, Scan Insertion, Physical Verification, LVS, Cadence synthesis, RTL-GDSII, Timing analysis and verification, Synthesis, PNR, Physical Design, DRC, Antenna, Cross talk, formal verification, IR-EM checks, Place And Route, Timing Analysis

Hard Macros (SerDes), Flip-Chip, PNR, Cadence Tools, Physical Implementation, FDSOI 22nm

layout verification , System Verilog, Tcl, design rules, Vlsi Design

PnR-Floorplan Macro placement, EM IR understanding and fixes, STA analysis, Util area reduction experiments, ECO cycle, Density Congestion Timing issues and fixes on lower tech nodes 5nm, Physical aware Synthesis using FC, PV closure