Jtag, C, Verilog, System Verilog, Uvm, SOC RTL Design Verification

Computer Architecture, C, Assembly Language, Vcs, Perl, Verilog, Python, System Verilog, Computer Engineering, Raven, UVM methodology, ACK, Microelectronics, Questa, Electrical Engineering

Debugging, Ovm, Verilog, System Verilog, Problem-solving skills, Functional Verification Coverage, Uvm, formal verification, DDR-PHY Design Verification, Design Verification of complex IPs, Low Power Verification, Gate Simulation

Unix, Bug Tracking, Makefile, Shell, Configuration Management, PERL, Python, Verification dashboarding tools, Random stimulus, ARM CPU, PCI Express, Uvm, Functional coverage, systemverilog, AMBA bus protocols, Ethernet bus protocols

C, Uart, Spi, Pcie, I2c, Axi, APB, AHB, simulation and debugging tools from Synopsys, Cadence, Siemens EDA, Uvm, systemverilog

Vcs, functional coverage assertions, Questa, Uvm, SVA, systemverilog

Usb, Fpga, Perl, Pcie, Python, high performance industry standard IO interfaces, emulator software environments, coverage driven verification, directed constrained-random tests, Uvm, systemverilog, AMBA, MIPI, formal verification, test bench infrastructure, transaction level modeling, AXI4

C, Perl, Computer Architecture, Ruby, Python, Assembly start up code, Makefiles, Stimulus generation, Uvm, Testbenches, Pre-silicon verification, Formal verification methods, Linker scripts, Post-silicon FPGA validation

Vcs, Xcelium, JasperGold, formal verification tools, assertion-based verification, Uvm, systemverilog, Questa, VC Formal, SVA, functional coverage

code coverage , Design Verification Engineer, Low Power Verification Engineer, Power-Aware Verification Engineer, ASIC Design Verification Engineer, systemverilog, Uvm, Constrained Random Verification, Gate-Level Simulation, Timing Simulation, PAGLS, Testbench Development, VIP Integration, Coverage Closure