test equipment , Usb, Pcie, Perl, Python, Tcl, HW testing, traffic analysers, high speed FPGA Design, FPGA Verilog design, high speed Ethernet, Xilinx FPGA technology and tools, test generators, debugging skills

Verilog, static timing analysis, Modelsim, Questa, Intel Quartus, synchronous design principles, Xilinx Vivado, RTL design methodologies, DO-254 design assurance process, Microsemi Libero, FPGA design flows, VHDL, Synthesis, timing closure techniques, FPGA design and development

hardware bring up , Tcl, C, FPGA Design, System Verilog, Python, Synthesis, Debug, test benches, Simulation, Rtl Design, Timing Closure, UVM verification flow, Verification

Fast Fourier Transform, Verilog, Digital Signal Processing, System Verilog, complex algebra, OFDM, FPGA development, Xilinx FPGA architectures, Rtl Design, AXI4 Stream Protocols, Vivado, baseband processing, AXI4 Lite, AXI4, linear algebra

Clock Domain Crossing (CDC), Static Timing Analysis (STA), Verilog, Intel Altera Quartus, Logic Analyzers, VHDL, Timing Constraints, AMD Vivado, FPGA Debugging, Oscilloscopes, Libero SoC

VHDL programming, Xilinx, FPGA development, hardware debugging, Intel Altera, Timing Closure, RFSoC, Vivado, Modelsim, LabVIEW FPGA, Rtl Design, Simulation

Hdl, VHDL

Pcie, Verilog, JESD204B, Isp, SERDES, Intel Quartus, systemverilog, Xilinx Vivado, Synthesis, VHDL, FFT, Video Processing Pipelines, MIPI Interfaces, CORDIC Algorithms, FIR Filters

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage