Verilog, Rtl Design, RTL Coding, Micro-architecture, systemverilog, RTL Design Engineer

Rtl Design, RTL quality checks, Micro-architecture design, SOC integration

Verilog, Fpga, VHDL, systemverilog, ASIC Design, Synthesis Tools, Timing Analysis, Verification Methodologies, Physical Design, low power design

Verilog, Rtl Design, Logic analyzers, systemverilog, DDR memory controller calibration, Calibration algorithms

Digital Logic Design, Rtl Design, SOC Integration, RTL quality checks, Constraints for Subsystem IP, ip design, Processor peripherals

conformal lec , Perl, Verilog, Python, Tcl, VC spyglass, IPXACT, LINT, Formality, VSI, UPF, 0in, RTL Coding, IORING, SoC IP level integration, Design Partitioning