Hard IP integration, Clock and Power distribution, STA setup convergence methodology, Power Integrity Analysis, Hierarchical design implementation, Automation scripts within STA tools, Timing Closure, Timing ECO Implementation, Floor Planning, Debugging skills in implementation issues, ASIC Physical implementation, Global signal planning, Physical convergence, Tweaker Primetime based ECO flows

Routing, Perl, Python, Tcl, Physical Design Methodology, power analysis, Cadence PD Tool Flow, EM Analysis, Power Integrity Concepts, Noise Analysis, Power Rail PDN Analysis, Current Density Check, Placement, Power Gating, Logic Synthesis, Clock Tree Synthesis, Voltage Islands, IR Verification

Physical Design, Timing Closure, Synthesis, RTL to GDSII, floorplanning, Constraints synthesis, Place And Route

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

redhawk , Ecos, floorplanning, low-power design methodologies, Tempus, Physical Verification, Voltus, Innovus, Physical Design, Genus, IR drop analysis, GDSII

Synopsys tool suite, physical design verification, IR EM analysis and resolution, ICV or Calibre tools, block level and full-chip physical verification methodology, full chip floor-planning and integration, complete physical design flow, block subsystem timing closure

Tcl Scripting, Linux, ASIC SoC Physical Design, EM IR analysis, Physical signoff

Sta, Innovus, Dft, primetime, ICC2, Cadence, Synopsys