Location: Bangalore / India (Hybrid / Onsite)
Company: Seminovaa Technologies Pvt. Ltd.
Experience: 4–7 years (Mandatory)
Domain: ASIC / SoC Physical Design
Important Note
This position is strictly for professionals with 4–7 years of hands-on Physical Design experience.
Freshers, college interns, and trainees will not be considered for this role.
About the Role
We are seeking a hands-on Physical Design Engineer with strong expertise in Clock Tree Synthesis (CTS), Static Timing Analysis (STA), EM/IR analysis, and physical signoff.
The role requires engineers who have worked on real silicon tapeouts and can independently contribute to timing and reliability closure in a services-driven environment.
Key Responsibilities
- Execute block-level Physical Design from placement through signoff.
- Perform Clock Tree Synthesis (CTS) including skew balancing, latency optimization, and clock QoR improvement.
- Drive Static Timing Analysis (STA) across MMMC corners, including setup/hold analysis and exception handling.
- Debug and resolve timing violations using ECO techniques (buffering, sizing, VT swaps, re-routing).
- Perform EM/IR and power integrity analysis and work with signoff teams to close violations.
- Execute and debug physical signoff checks including DRC, LVS, Antenna, Density, and reliability checks.
- Collaborate with PD, STA, and signoff teams to deliver tapeout-quality databases.
- Follow best practices for PD execution, documentation, and design quality.
Required Qualifications (Mandatory)
- Bachelor's or Master's degree in Electrical Engineering, Electronics & Communication Engineering, VLSI, or a related discipline.
- 3–5 years of hands-on experience in ASIC / SoC Physical Design.
- Strong working experience in CTS, STA, EM/IR analysis, and physical signoff.
- Proficiency in industry-standard tools such as:
- Synopsys: Fusion Compiler / ICC2, PrimeTime, IC Validator
- Cadence: Innovus, Tempus, Voltus (or equivalent tools)
- Good understanding of advanced technology nodes (7nm and below preferred).
- Working knowledge of Linux and TCL scripting.
Preferred Qualifications
- Exposure to high-frequency designs and tight timing budgets.
- Experience handling macro-heavy blocks and congestion-prone designs.
- Prior experience in semiconductor product or design services companies.
- Ability to independently own block-level timing and signoff closure under guidance.
Educational Qualification (Mandatory)
- Bachelor's degree (B.E. / B.Tech) in Electrical Engineering, Electronics & Communication Engineering, Electronics, VLSI, or a closely related discipline from a recognized university.
- Candidates must have completed their degree through full-time academic programs.
Who Should NOT Apply
- Fresh graduates or college interns
- Candidates with only academic or training-based exposure
- Profiles without hands-on CTS / STA / EMIR / signoff experience
- Pure front-end or verification-only profiles
Why Join Seminovaa
- Work on advanced-node silicon programs
- Exposure to end-to-end PD, timing, and signoff ownership
- High-impact role in a fast-growing semiconductor services company
- Strong technical growth path into senior PD roles
How to Apply
Interested candidates may apply via LinkedIn or share their resume at:
[Confidential Information]
