code coverage , closure , Ovm, Perl, Tcl Scripting, Verilog, SDF, automation, Specman, SV, assertions development, constraint randomization, RTL, Uvm, GLS, formal verification, eRM methodology, test-bench development, HVL

Logic Design, DDR, AMS verification, system level design, Mixed Signal IP design, AMS design techniques, High-speed circuits, Lab debugs on AMS IPs, Tx Rx CTLE Amplifiers Samplers, Analog Mixed Signal design, HBM technologies, Circuit architecture, SERDES

automation, Ovm, Tcl Scripting, Verilog, Perl, test-bench development, GLS, Uvm, RTL, SV, SDF sim debug, Specman, HVL, functional and code coverages, closure constraint randomization, assertions development, eRM methodology, formal verification

System Verilog, Uvm, Environment Development, Design Verification, Functional Verification, Test Plan Generation