Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA

Soc Architecture, Shell, Perl, System Verilog, Python, Cadence Xcelium, Simulation Tools, Uvm, Synopsys VCS, digital design concepts, Axi, AMBA, APB, AHB, debugging using waveforms and logs

Cpu, Ethernet, Pcie, Debugging, DDR, Uvm, Assertions, SoC Integration, SV, Coverage Closure, Complex Verification Flows, RISC-V, formal verification, IP Sub-System SoC DV Testbench Development

Scripting Languages, Sed, Awk, Perl, ARM processor based SoC architecture, ASIC design flow, ASIC verification methodologies, C Assertions coding, multi-core multi-layer APIs, functional coverage, SV-UVM, constraint random test generation, UVM assertion based coverage driven verification, ARM based SOC software framework

analog circuits , Unix Environment, DDR, shell scripting, Verilog, Python, Models, memory subsystems, digital design processes, simulation debugging, RTL, Uvm, top-level integration, systemverilog, Schematics, VerilogAMS

C, Coding, Performance Modeling, low power design verification techniques, coverage planning, power management verification, testbench development, systemverilog, coverage closure, GLS power aware verification, ACPI standards, post-si verification, Validation