power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

Innovus, Physical Design

Python, Tcl, floorplanning, LVS, Logical Equivalence, Clock CTS, Physical Verification, Synthesis, Timing Analysis, EDA Tools, ERC, DRC, Budgeting, Place And Route

Docker, Python, AI ML background, Optimization, SOC domain, graph algorithms, combinatorial algorithms, geometry packages such as shapely

routing, block level place and route, floor-planning, Power grid analysis, Extraction, Physical Synthesis, Netlist, full chip implementation, GDS flow, STA timing, flow-automation, Signal Integrity, clock tree optimization, formal verification, Dft, Timing Constraints, Regression, digital design automation, Timing Closure, CTS IO timing, RTL-to-GDSII, Antenna fixing

Routing, Perl, Python, Tcl, Physical Design Methodology, power analysis, Cadence PD Tool Flow, EM Analysis, Power Integrity Concepts, Noise Analysis, Power Rail PDN Analysis, Current Density Check, Placement, Power Gating, Logic Synthesis, Clock Tree Synthesis, Voltage Islands, IR Verification

Full chip, SOC design, Sub micron designs

Prometheus, Apache Tomcat, Grafana, Docker, Terraform, MySQL, Python, Java, Newrelic, Cortex, Datadog, Jenkins, Linux, Ansible, Splunk, Puppet, Azure, Kubernetes, Chef, Go, Groovy DSL, cfengine, Cloud Formation Templates, AKS, EKS