Physical Design Engineer

power optimization , Perl, Scripting, Python, Tcl, Cadence, Mentor, Timing Analysis, Physical Design, Signal Integrity, EDA Tools, Synopsys

Python, Routing, Perl, Tcl, physical design methodologies, floor-planning, CTS, Synopsys Fusion Compiler, PPA tradeoffs, LVS, Calibre, Physical Verification, Extraction, StarRC, floor plan synthesis, Synthesis, Apache Redhawk, CPU physical design, EM, Ir, signoff, Place And Route, Timing Closure, DRC, Cadence PrimeTime, Placement

redhawk , Perl, Tcl, Dc, Deep sub-micron designs, Pt, Logic equivalence checking, Formality, VSLP, LVS, ICC, STA timing, Physical Design, Calibre, Timing Closure, Synthesis, SOC design, DRC, Place And Route, Low Power checking

Routing, Perl, Python, Tcl, Physical Design Methodology, power analysis, Cadence PD Tool Flow, EM Analysis, Power Integrity Concepts, Noise Analysis, Power Rail PDN Analysis, Current Density Check, Placement, Power Gating, Logic Synthesis, Clock Tree Synthesis, Voltage Islands, IR Verification

power optimization , C, Linux, Perl, Unix Shell, Tcl, Advanced STA Concepts, Physical Design Flow, Block level PnR convergence, Timing Convergence, Cadence Innovus, LVS, PTSI Tempus, Physical Verification, formal verification, Timing Closure, DRC, PDN, Floor-planning, Place And Route, Synopsys ICC2