Shell, Tcl Scripting, Python, Routing, Perl, Sta, CTS, Signoff, OCV, primetime, Fusion Compiler, Crosstalk, Tempus, Cadence Innovus, Signal Integrity, LVS, IR Drop, Physical Verification, MCMM, POCV, Setup Hold, RTL-to-GDSII Physical Design flow, floorplanning, Post-route Optimization, Placement Optimization, EM, Power Planning, Eco, Timing Closure, DRC, AOCV, Synopsys ICC2

Routing, Perl, Python, Tcl, CTS Clock Optimization, floorplanning, Placement Optimization, IR EM, Synopsys Fusion Compiler, Cadence Innovus, Physical Signoff, Power Planning, Eco, MMMC, PPA Optimization, STA Timing Closure, VLSI Physical Design, Synopsys ICC2

ML optimization tools (DSO.ai), CTS and routing, Timing-driven placement, PPA Optimization, floorplanning, Hierarchical physical design, RTL-to-GDS implementation flow, Synopsys Fusion Compiler, Pin assignment, Timing budgeting

Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design

Physical Design, Timing Closure, Power Planning, Deep sub-micron technology issues, Floor Planning, Signal integrity analysis, Place And Route

Clp, Sta, Timing Constraints, RTL synthesis, LEC, low-power design concepts

Routing, Sta, CTS, floorplanning, EM, Ir, LVS, Physical Implementation, Synthesis, Physical Design, Placement, Si, DRC, RTL Netlist, Timing Closure, Tape-out, Power Domains, GDSII, Hierarchical Designs

Routing, power analysis, Physical Verification, Physical Design, floorplanning, Timing Closure, Placement, DRC, LVS, Signal Integrity, Rtl Design

routing, Sta, CTS, ASIC PD methodologies, digital design fundamentals, Extraction, Floor Planning, PNR, Placement, EM IR closure, signoff