Block level and Top-level physical implementation, Place and Route processes, Physical Design, Synthesis for high-speed designs

Routing, Python, Tcl, CTS, floorplanning, Placement Optimization, Antenna Density, LVS, Power Planning, IC Validator, Calibre, Physical Verification, Signoff Closure, Physical Design, ERC, Timing Closure, ECO Implementation, DRC

routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows

Perl scripting, PrimeTime-SI, primetime, Antenna Checks, LVS, Substrate Bias, IR Drop Analysis, low power design, Physical Verification, Physical Design, Timing Closure, Synopsys Physical Design tools, Power Gating, Floor Planning, DRC, Voltage Islands

Physical Design Engineer, Physical Design, Physical verification closure

Static Timing Analysis, Frontend, Asic, Timing Closure, Physical Verification

static timing analysis, routing, Innovus, LVS, Parasitic Extraction, Fusion Compiler, DRC, Placement, floorplanning, Clock Tree Synthesis, ICC2

Tcl, PERL, Cadence, Floor Planning, SI Aware Routing, Synopsys, Voltage Islands, Timing Analysis Closure, ECO Tasks, Physical Verification, Timing Optimization, Substrate-bias Techniques, Asic Physical Design, Power Gating, Physical Design, Timing Closure on High Speed Interfaces, low power design, IR Drop Analysis, Antenna Checks, Signal Integrity Closure