Physical Design Engineer
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He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias.
Role: Physical Design / Layout Engineer
Industry Type: Electronic Components / Semiconductors
Department: Engineering - Hardware & Networks
Employment Type: Full Time, Permanent
Role Category: Hardware
Education
UG: Any Graduate
PG: Any Postgraduate
Job ID: 107087181
Skills:
static timing analysis, Synthesis, verification methodologies, design optimization techniques, low-power design methodologies, Power Planning, Place And Route, FC Innovus, Clock Tree Synthesis
Skills:
C, Routing, Perl, Tcl, Clock Planning, primetime, floorplanning, ICC2, LEC, Calibre, Innovus, Physical Verification, Placement, Timing Closure, Physical Design Implementation, EDA Tools
Skills:
hardware engineering , automation, physical design methodologies, lower technology nodes, power gating, sign-off optimizations, multi-voltage domains, deep sub-micron technology, Netlist2GDS, ASIC design flows, Floorplan, Circuit Design, device physics
Skills:
routing, Verilog, Floor Planning, VHDL, Placement, Physical Verification, Clock Tree Synthesis, RTL to GDS flows
Skills:
Static Timing, Routing, Physical Verification, Synthesis, Power Efficiency, Custom Clocking, Physical Design, floorplanning, Placement, Formal Equivalency, IR-Drop
