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Bengaluru, India

Skills:

VcsDDRPcieDebuggingPythonUsbFPGA DesignEthernetTclFPGA toolchainslogic analyzersOscilloscopesclock domain crossingIntel QuartusResource OptimizationVHDLin-circuit emulatorsLattice DiamondTiming AnalysissystemverilogXilinx VivadoQuestaModelsimdigital system designHardware Verification

Early Applicant
Bengaluru, India

Skills:

memory controllers UartSpiHdl LanguagesPcieVerilogI2cUnix SystemsOtnUvmMicrosemi FPGAssystemverilogEthernet-based protocolsAxiquartusVHDLscripting toolsVivadoVMMLibero

Early Applicant
Bengaluru, India

Skills:

FPGA DesignVerilogFPGA debuggingVHDLAMD Vivadologic analyzersIntel Altera QuartusOscilloscopesLibero SoC

Early Applicant
Bengaluru, India

Skills:

VHDL programmingXilinxFPGA developmenthardware debuggingIntel AlteraTiming ClosureRFSoCVivadoModelsimLabVIEW FPGARtl DesignSimulation

Early Applicant
Bengaluru, India

Skills:

rtl development nand flash TclVerilogFPGA DesignPythonBashPcieIP IntegratorVivado Design SuiteVHDLChipScope ILAEmbedded SystemsXilinx FPGAs

Early Applicant
Bengaluru, India

Skills:

Tcl ScriptingDoorsKnowledge of Hardware Board and different components like ADC DAC Serial MemoryDO-254 development processElectronics Electrical EngineeringHardware system design knowledge of digital logicRTL development using VHDLFPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim QuestasimFPGA Synthesis Place and RouteDeveloping timing constraints solving CDC issues timing analysis and timing closures for FPGARequirement analysis and validationDifferent bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAGFPGA design tools like Libero

Early Applicant
Bengaluru

Skills:

DoorsTcl ScriptingFPGA Synthesis Place and RouteDO-254 development processRTL development using VHDLHardware system design knowledge of digital logicDifferent bus protocols like I2C SPI QSPI UART AXI DDR3 4 PCIe JTAGFPGA verification developing Test case Test procedures Test bench debug and simulation using Modelsim QuestasimDeveloping timing constraints solving CDC issues timing analysis and timing closures for FPGAFPGA design tools like LiberoElectronics Electrical EngineeringKnowledge of Hardware Board and different components like ADC DAC Serial Memory

Early Applicant
Bengaluru, India

Skills:

TclVerilogPythonPerlVHDLsystemverilogVivadoquartus

Early Applicant
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