Design Verification, ASIC Design, Verification Planning, systemverilog, Rtl Design

Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

power optimization , Cpu, Noc, Tcl, Verilog, Networking, System Verilog, Python, Perl, LINT, Synthesis, High-Level Synthesis, Micro-architecture Development, Peripheral Subsystems, cdc, RTL Coding, Formal Verification Methodology, Timing Closure, Shell-scripting, power analysis

Area and power-efficient complex RTL design, High performance low latency high bandwidth design techniques, Low power microarchitecture techniques, Experience with simulators and waveform debug tools, Verilog RTL logic design, Knowledge of logic design principles including timing and power implications

rtl development , power delivery , Verilog, ASIC design flow, Dft, mixed-signal chips, Behavioral Circuit Modeling, Timing Analysis, Custom Digital Design, power management solutions, System-Verilog