Pcie, SV, CXL, PCI-E, LPDDR, UCIe, DDR4, Uvm, USB 3.0

test environments , C, Soc Architecture, Test Cases, Shell, Verilog, Python, industry-standard simulators, Mixed signal designs, SV, regression systems, Uvm, revision control systems, verification testbenches

Usb, DDR, Shell, Perl, Ethernet, Python, Emulation, UVM methodology, high-speed interfaces PCIe, systemverilog, scoreboards, industry-standard simulators and tools, formal verification, ASIC SoC architecture, functional coverage assertions, debugging skills, low-power verification UPF, SVA

Mac, Pcie, Verilog, Ethernet, high-speed interfaces, Siemens Veloce, Palladium, Cadence, systemverilog, full-chip verification, SoC-level integration, UVM-based verification environments, SoC Verification, ZeBu, SERDES, D2D, Synopsys, functional coverage

High Speed Serial Interfaces PCIe Gen 3 4 or USB or MIPI, Synopsys VCS, C SV, Foundry Porting Experience Technology Library Conversion Related Changes Verification, Memory Interfaces DDR or HBM, Technical Documentation Testbench Specification Test Plan Specification, Third Party VIP Integration, Interconnect Protocols AHB AXI APB, SV UVM, Cadence Incsive, Coverage Closure Code Functional and Toggle, SOC Interfaces GPIO SPI I2C UART

Cpu, Ethernet, Pcie, Debugging, DDR, Uvm, Assertions, SoC Integration, SV, Coverage Closure, Complex Verification Flows, RISC-V, formal verification, IP Sub-System SoC DV Testbench Development

bandgap references , mixed signal design architectures, verification debug, Uvm, SV, power management, DACs, analog mixed signal behavioral modeling, ADCs, full chip verification, self-checking testcases, Oscillators, verification environment development, SERDES, Pll